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Data Sheet 26185.116B
A6833
DABiC-5 32-Bit Serial Input Latched Sink Drivers
Designed to reduce logic supply current, chip size, and system cost, the A6833 integrated circuits offer high-speed operation for thermal printers. These devices can also be used to drive multiplexed LED displays or incandescent lamps within their 125 mA peak output current rating. The combination of bipolar and MOS technologies gives the A6833 smart power ICs an interface flexibility beyond the reach of standard buffers and power driver circuits. These 32-bit drivers have bipolar open-collector npn Darlington outputs, a CMOS data latch for each of the drivers, a 32-bit CMOS shift register, and CMOS control circuitry. The high-speed CMOS shift registers and latches allow operation with most microprocessor-based systems. Use of these drivers with TTL may require input pull-up resistors to ensure an input logic high. CMOS serial data outputs permit cascading for applications requiring additional drive lines. The A6833 is supplied in a 44-lead plastic chip carrier (quad pack), intended for surface mounting on solder lands with 0.050 in. (1.27 mm) centers. These devices are lead (Pb) free, with 100% matte tin plated leadframes.
41 40 39 38 37 36 35 34 33 32 31 30 29 21 22 23 24 25 26 27 18 19 20 28
A6833SEP 44-pin PLCC
44 43 42 6 5 4 3 2 1
7 8 9 10 11 12 13 14 15 16 17
FEATURES
3.3 V to 5 V logic supply range To 10 MHz data input rate 30 V minimum output breakdown Darlington current-sink outputs Low-power CMOS logic and latches
ABSOLUTE MAXIMUM RATINGS
Output Voltage, VOUT .........................................30 V Logic Supply Voltage, VDD...................................7 V Input Voltage Range, VIN ..............-0.3 V to VDD +0.3 V Continuous Output Current (each output), IOUT ... 125 mA Package Power Dissipation, PD A6833SA................................................ 3.5 W* A6833SEP .............................................. 2.5 W* Operating Temperature Range Ambient Temperature, TA ............-20C to +85C Storage Temperature, TS ..........-55C to +150C *Derate linearly to 0 W at +150C. Caution: CMOS devices have input-static protection, but are susceptible to damage when exposed to extremely high static-electrical charges.
Schmitt trigger inputs for improved noise immunity
APPLICATIONS
Thermal printheads Multiplexed LED displays Incandescent lamps
Use the following complete part numbers when ordering:
Part Number A6833SEP-T Pins 44 Package PLCC
Data Sheet 26185.116B
A6833
DABiC-5 32-Bit Serial-Input Latched Sink Drivers
Functional Block Diagram
C LOC K S E R IAL DATA IN 32-B IT S HIF T R E G IS T E R
V DD S E R IAL DATA OUT
S T R OB E LAT C HE S OUT P UT E NAB LE LOG IC G R OUND
S UB
MOS B IP OLAR
OUT1
OUT 2 OUT3
OUT 30 OUT31 OUT32 P OWE R G R OUND
Typical Input Circuit
VDD
Typical Output Driver
OUT
IN
SUB
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115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
2
Data Sheet 26185.116B
A6833
DABiC-5 32-Bit Serial-Input Latched Sink Drivers
ELECTRICAL CHARACTERISTICS1 Unless otherwise noted: TA = 25C, logic supply operating voltage Vdd = 3.0 V to 5.5 V
Vdd = 3.3 V Characteristic
Output Leakage Current Collector-Emitter Saturation Voltage Input Voltage Input Current Serial Data Output Voltage Maximum Clock Frequency2 Logic Supply Current Output Enable-to-Output Delay Strobe-to-Output Delay Output Fall Time Output Rise Time Clock-to-Serial Data Out Delay
1Positive
Vdd = 5 V Typ.
- - - - - < 0.01 < -0.01 4.75 0.15 - - - - - - - - - 50
Symbol
ICEX VCE(SAT) VIN(1) VIN(0) IIN(1) IIN(0) VOUT(1) VOUT(0) fc IDD(1) IDD(0) tdis(BQ) ten(BQ) tp(STH-QL) tp(STH-QH) tf tr tp(CH-SQX)
Test Conditions
VOUT = 30 V IOUT = 50 mA IOUT = 100 mA
Min.
- - - 2.2 -
Typ.
- - - - - < 0.01 < -0.01 3.05 0.15 - - - - - - - - - 50
Max. Min.
10 0.7 1.0 - 1.1 1.0 -1.0 - 0.3 - 2.0 100 1.0 1.0 1.0 1.0 500 500 - - - - 3.3 - - - 4.5 - 10 - - - - - - - - -
Max.
10 0.7 1.0 - 1.7 1.0 -1.0 - 0.3 - 2.0 100 1.0 1.0 1.0 1.0 500 500 -
Units
A V V V V A A V V MHz mA A s s s s ns ns ns
VIN = VDD VIN = 0 V IOUT = -200 A IOUT = 200 A One output on, IOUT = 100 mA All outputs off VCC = 50 V, R1 = 500 , C1 30 pF VCC = 50 V, R1 = 500 , C1 30 pF VCC = 50 V, R1 = 500 , C1 30 pF VCC = 50 V, R1 = 500 , C1 30 pF VCC = 50 V, R1 = 500 , C1 30 pF VCC = 50 V, R1 = 500 , C1 30 pF IOUT = 200 A
- - 2.8 - 10 - - - - - - - - -
2Operation
(negative) current is defined as conventional current going into (coming out of) the specified device pin. at a clock frequency greater than the specified minimum value is possible but not warranteed.
Truth Table
Serial Shift Register Contents Data Clock Input Input I1 I2 I3 ... IN-1 IN H L X H L R1 R2 ... R1 R2 ... X X ... RN-2 RN-1 RN-2 RN-1 RN-1 RN X X PN-1 PN Serial Data Strobe Output Input RN-1 RN-1 RN X PN L H R1 R2 R3 ... P1 P2 P3 ... X
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
Latch Contents I1 I2 I3 ... IN-1 IN
Output Enable Input
Output Contents I1 I2 I3 ... IN-1 I N
R1 R2 R3 ... X P1 P2 P3 ...
RN-1 RN PN-1 PN X X H L P1 P2 P3 ... PN-1 PN H H H ... H H
X
X
...
www.allegromicro.com
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
3
Data Sheet 26185.116B
A6833
DABiC-5 32-Bit Serial-Input Latched Sink Drivers
Timing Requirements and Specifications
(Logic Levels are VDD and Ground)
C C LOC K A S E R IAL DAT A IN DAT A
50%
B
50%
t p(C H-S QX) S E R IAL DAT A OUT D S T R OB E
50% 50%
DAT A E
OUT P UT E NAB LE
HIG H = ALL OUT P UT S E NAB LE D t p(S TH-QH) t p(S T H-QL)
90%
OUT N
DAT A
10%
LOW = ALL OUT P UT S B LANK E D (DIS AB LE D) OUT P UT E NAB LE
50%
t en(B Q) tr t dis (B Q) OUT N
10%
tf
90% 50%
DAT A
Key A B C D E
Description Data Active Time Before Clock Pulse (Data Set-Up Time) Data Active Time After Clock Pulse (Data Hold Time) Clock Pulse Width Time Between Clock Activation and Strobe Strobe Pulse Width
Symbol tsu(D) th(D) tw(CH) tsu(C) tw(STH)
Time (ns) 25 25 50 100 50
NOTE: Timing is representative of a 10 MHz clock. Higher speeds may be attainable; operation at high temperatures will reduce the specified maximum clock frequency. Serial Data present at the input is transferred to the shift register on the logical 0 to logical 1 transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform. Information present at any register is transferred to the respective latch when the STROBE is high (serial-to-parallel conversion). The
latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that the OUTPUT ENABLE input be low during serial data entry. When the OUTPUT ENABLE input is low, the output sink drivers are disabled (OFF). The information stored in the latches is not affected by the OUTPUT ENABLE input. With the OUTPUT ENABLE input high, the outputs are controlled by the state of their respective latches.
www.allegromicro.com
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
4
Data Sheet 26185.116B
A6833
DABiC-5 32-Bit Serial-Input Latched Sink Drivers
A6833SEP
SERIAL DATA OUT POWER GROUND OUTPUT ENABLE
SERIAL DATA IN
STROBE
LOGIC SUPPLY CLOCK
OUT32
41
OUT1
NC
CLK 44
43
OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8 OUT 9 OUT10 OUT11 OUT 12
OE 42
VDD 1
ST 4
40
5
6
3
2
NC
7 8 9 10
39 38 37 36
OUT31 OUT30 OUT29 OUT28 OUT27 OUT26 OUT25 OUT24 OUT23 OUT22 OUT21
REGISTER
REGISTER
LATCHES
LATCHES
11 12 13 14 15 16 17
35 34 33 32 31 30 29
SUB
OUT13 19
OUT14 20
OUT15 21
OUT16 22
LOGIC GROUND 23
OUT17 24
OUT18 25
OUT19 26
OUT20 27
NC 18
NC 28
www.allegromicro.com
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
5
Data Sheet 26185.116B
A6833
DABiC-5 32-Bit Serial-Input Latched Sink Drivers
A6833SEP
Dimensions in Inches (controlling dimensions)
28 18
29 0.319 0.291 0.021 0.013 0.695 0.685 0.656 0.650 0.319 0.291 0.050
BSC INDEX AREA
17
0.032 0.026
39
7
40 0.020
MIN
44
1
2
6
0.656 0.650 0.695 0.685
Dwg. MA-005-44A in
0.180 0.165
Dimensions in Millimeters (for reference only)
28 18
29 8.10 7.39 0.533 0.331 17.65 17.40 16.662 16.510
INDEX AREA
17
0.812 0.661
8.10 7.39 1.27
BSC
39
7
40 0.51
MIN
44
1
2
6
4.57 4.20
16.662 16.510 17.65 17.40
Dwg. MA-005-44A mm
NOTES: 1. Exact body and lead configuration at vendor's option within limits shown. 2. Lead spacing tolerance is non-cumulative.
www.allegromicro.com
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
6
Data Sheet 26185.116B
A6833
DABiC-5 32-Bit Serial-Input Latched Sink Drivers
The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.
Copyright(c)2003, 2004, 2005 AllegroMicrosystems, Inc.
www.allegromicro.com
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
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